Steven is the FPGA Design Engineer within the ESS Detector Group. He is based at Daresbury Laboratory in the United Kingdom, working alongside partners from the Science and Technology Facilities Council.
Prior to ESS, he has worked in both public and private sector environments, where he performed technical liaison functions as well as engineering development. He has particular experience in developing and integrating DSP and packet-processing functionality on FPGAs, both within an embedded and high-performance computing context.
- Field Programmable Gate Arrays
- Digital Signal Processing
- IP Networking
- 2016 - present FPGA Design Engineer, ESS
- 2012 - MEng in Electronic Engineering, University of Durham